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| QLogic Corporation FAS209 Fast Architecture SCSI Data Sheet Features s s s s s s s s s s s s s s s s s s s Compliance with ANSI SCSI-2 standard X3.131-1994 and SCSI-1 Compliance with ANSI X3T10/855D SCSI-3 parallel interface (SPI) standard Compliance with ANSI SCSI configured automatically (SCAM) protocol levels 1 and 2 Synchronous data transfers up to 10 Mbytes/sec fast SCSI and 5 Mbytes/sec normal SCSI Asynchronous data transfers up to 7 Mbytes/sec Up to 12 Mbytes/sec DMA burst transfer rate Clock rates up to 40 MHz Supports hot plugging Programmable active negation Low-input capacitance Programmable split-bus architecture DMA interface options Two bus configurations On-chip, 48-mA, single-ended drivers and receivers Parity pass-through on FIFO data Initiator and target roles SCSI sequences implemented without microprocessor intervention Part-unique ID code Eight-bit, single-ended SCSI operations bus, minimizing board space requirements. The FAS209's highly integrated structure provides users with numerous benefits. Initiator and target roles are supported; therefore, the FAS209 can be used in both host adapter and peripheral applications. The FAS209 performs such functions as bus arbitration, selection of a target, or reselection of an initiator. It handles message, command, status, and data transfer between the SCSI bus and the chip's 16-byte internal FIFO or a buffer memory. The above functions are internal processes performed by the FAS209 chip without microprocessor intervention. SCAM Implementation The FAS209 supports levels 1 and 2 of the SCAM protocol. (Refer to the latest revision of X3T10/855D, Annex B.) The SCAM protocol requires direct access and control over the SCSI data bus and several of the SCSI phase and control signals. The majority of the SCAM protocol can be implemented in firmware at microprocessor speeds. The following SCAM features are supported in the hardware: s Arbitration without an ID s Slow response to selection with an unconfirmed ID s Detection of and response to SCAM selection Bus Configuration The FAS209 split-bus architecture separates the two high-traffic information buses of the system, providing maximum efficiency and throughput. The versatile bus architecture supports various microprocessor and DMA bus configurations, including those listed below: s Microprocessor interface via the PAD bus or the DB bus s Concurrent microprocessor and DMA accesses s PAD bus selectable as a data-only bus Product Description The FAS209 is a high-performance SCSI interface chip designed to maximize transfer rates over the SCSI bus. It is the enhanced SCSI follow-on to QLogic's FAS216 SCSI processor chip, adding active negation and SCAM to the FAS216 design. The FAS209 supports bidirectional, single-ended SCSI operations. The block diagram of the FAS209 is illustrated in figure 1. The FAS209 maximizes transfer rates by sustaining asynchronous data rates of up to 7 Mbytes/sec and fast, synchronous data transfer rates of 10 Mbytes/sec. The normal 5 Mbytes/sec synchronous transfer rate is also supported. With its on-chip, 48-mA, single-ended drivers and receivers, the FAS209 can connect directly to the SCSI 53209-580-00 C FAS209 1 QLogic Corporation SCSI DATA DB BUS FIFO COMMAND TRANSFER COUNT TRANSFER COUNTER REGISTER BUS (OUT) REGISTER BUS (IN) SELECT/RESELECT BUS ID SELECT/RESELECT TIMEOUT SEQUENCERS SYNC PERIOD SYNC OFFSET/ SYNC ASSERT/ SYNC DE-ASSERT INTERRUPT STATUS SEQUENCE STEP SCSI CONTROL CLK CONVERSION CONFIGURATION PAD BUS TEST Figure 1. FAS209 Block Diagram FAS209 bus configuration is selected by pulling the MODE pin up or down, as shown in table 1. Table 1. Bus Modes Mode No. 0 1 MODE Pin 0 1 Register Data DB bus PAD bus DMA Data DB bus DB bus Configuration Single bus, 8-bit DMA Split bus, 8-bit DMA Pins that support the microprocessor and DMA interfaces and other chip operations are shown in figure 2. DMA Interface All FAS209 DMA activity occurs over the DB bus. The path is eight bits wide. The DB bus consists of the data parity pin DBP0 and data pins DB7-0. Data is transferred on DB7-0 on writes to and reads from the SCSI bus. DACK must be active during DMA accesses. The transfer direction is determined by the type of command executed by the chip. DBWR strobes data into the chip. DMA read data is driven by the chip when DACK is true. Microprocessor Interface Microprocessor interface to the FAS209 occurs over the PAD bus or the DB bus. Both interfaces allow the microprocessor to read and write to all the internal chip registers, including the FIFO. In single-bus mode (bus configuration mode 0), the PAD bus is not used and the microprocessor must arbitrate with other controllers for use of the DB bus. In split-bus mode (bus configuration mode 1), the PAD bus is dedicated to the microprocessor interface. Packaging The FAS209 is available in a 64-pin plastic quad flat pack (PQFP), part number 2405055; and a thin quad flat pack (TQPF), part number 2405095. The pin diagrams are shown in figures 2 and 4. Package dimensions are shown in figures 3 and 5. The FAS209 pins that support microprocessor interfaces and other chip operations are shown in figure 6. 2 FAS209 53209-580-00 C QLogic Corporation DBWR DACK DREQ VSS DB1 DB0 VDD VSS WR 34 NC RD NC A2 A1 A0 35 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 DB2 DB3 DB4 DB5 DB6 DB7 DBP0 VSS PAD0 PAD1 PAD2 PAD3 PAD4 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 36 33 NC CK CS A3 32 31 30 29 28 27 RESET INT MODE VSS RST ATN IO CD MSG VSS ACK REQ BSY FAS209 64-PIN PQFP 26 25 24 23 22 21 20 VDD NC NC VSS SD1 VSS PAD5 PAD6 PAD7 NC = NO CONNECT Figure 2. FAS209 PQFP Pin Diagram 23.5 MIN 24.15 MAX 19.8 MIN 20.2 MAX PIN 51 PIN 52 PIN 33 A SDP PIN 32 17.5 MIN 18.15 MAX 4 TYP 13.8 MIN 14.2 MAX INDEX MARK PIN 20 0.80 0.2 +0.1 0.15 -0.05 2.7 0.2 3.18 MAX VSS SD0 SD2 SD3 SD4 SD5 SD6 SD7 SEL 0.25 MIN 0.45 MAX 1.0 BSC 0.09 MIN 0.68 MAX PIN 64 PIN 1 PIN 19 DETAIL A NOTE: ALL DIMENSIONS ARE IN MILLIMETERS. Figure 3. 64-Pin PQFP Mechanical Drawings 53209-580-00 C FAS209 3 QLogic Corporation DBP0 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 PAD0 VSS DB7 DB6 DB5 DB4 DB3 DB2 50 63 58 57 56 55 54 53 52 51 61 60 64 62 59 49 48 47 46 45 44 43 42 DB1 PAD7 VDD VSS SD0 NC SD1 SD2 SD3 VSS SD4 SD5 SD6 SD7 SDP VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DB0 NC VSS DBWR DACK DREQ VSS VDD CLK A3 A2 A1 A0 CS RD WR FAS209 64-PIN TQFP 41 40 39 38 37 36 35 34 33 SEL RESET ACK CD NC REQ RST MODE VSS MSG BSY ATN NC = NO CONNECT Figure 4. FAS209 64-Pin TQFP Pin Diagram 16.0 0.2 PIN 64 PIN 1 14.0 0.1 PIN 49 A INDEX MARK PIN 48 VSS INT 0.175 + 0.025 1.4 + 0.05 16.0 0.2 14.0 0.1 4 TYPICAL NC IO +0.08 0.37 -0.07 0.60 + 0.15 PIN 33 0.80 BSC DETAIL A 0.10 + 0.05 PIN 16 PIN 17 PIN 32 NOTE: ALL DIMENSIONS ARE IN MILLIMETERS. Figure 5. FAS209 TQFP Mechanical Drawings 4 FAS209 53209-580-00 C QLogic Corporation FAS209 4 MICROPROCESSOR AND DMA INTERFACE 8 A3-0 CS DACK DB7-0 DBP0 DBWR DREQ INT MODE 8 PAD7-0 RD WR 29 RESET POWER AND GROUND 10 NO CONNECT 5 5 64 2 8 VDD VSS CK CLOCK RESET 1 ACK ATN BSY CD IO MSG REQ RST SD7-0 SDP SEL 18 8 SCSI INTERFACE 1 Figure 6. FAS209 Functional Signal Grouping Electrical Characteristics Table 2. Operating Conditions Symbol VDD IDDa IDD TA Description Supply voltage Supply current (static IDD) Supply current (dynamic IDD) Ambient temperature 0 Minimum 4.75 Maximum 5.25 TBD TBD 70 Unit V mA mA oC Table Notes Conditions that exceed the operating conditions but are within the absolute maximum stress ratings may cause the chip to malfunction. Capacitance in and out (CIN, COUT) is 10 pF maximum for all pins, except SCSI pins. aStatic IDD refers to all inputs at VDD, all outputs open circuit, and all bidirectional pins configured as inputs. 53209-580-00 C FAS209 5 QLogic Corporation 6 FAS209 53209-580-00 C QLogic Corporation 53209-580-00 C FAS209 7 QLogic Corporation Specifications are subject to change without notice. QLogic is a trademark of QLogic Corporation. (c)February 14, 1997 QLogic Corporation, 3545 Harbor Blvd., Costa Mesa, CA 92626, (800) ON-CHIP-1 or (714) 438-2200 8 FAS209 53209-580-00 C |
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